Job Details:

Job Description:
Foundational IP team under Foundry Design Technology Platform group has primary focus of Standard Cell Library development to support both Intel Product Teams and External customers. The team is looking for a highly motivated and experienced individual to lead the library development, and optimization of standard cell libraries to enable best-in-class IP and product design on all generations of Intel technology.

Responsibilities include but are not limited to the following:

• Leads and manages the strong and vital organization of the Standard Cell Library team in Malaysia that spans across all functions of the Standard Cell Library organization.
• Collaborates and work closely with the Standard Cell Library Staff members who own various libraries and functions.
• Responsible for enabling teams to execute through clear goal setting, facilitating work, maintaining accountability, driving team results, and applying differentiated performance management.
• Works to continuously improve organization and development processes across all areas of design to improve efficiency and achieve quality standards.

As a technical lead, you are responsible for leading the standard cell library development and optimization activities with active collaboration with process technologists, product design and IFS stakeholders, and EDA vendors to achieve best-in-class cell/block level PPA and competitive EoU (Ease of Use) through DTCO (Design-Technology Co-Optimization).

Assume a leadership role managing a group of engineers, leaders, and managers in circuit design development, layout design development, extraction/characterization execution activities, FE/BE modeling, reliability/IR drop characterization, driving automation, and standardization of standard cell library development and validation flows. Supporting development and delivery of various process and PDK (Process Design Kits) production standard cell contents.

Our goal is to define, design, develop, and deliver best-in-class production standard cell libraries. Work on designing and characterizing standard cell libraries in the latest technology node, while also advancing the concepts of circuit design at the transistor level, as well as modeling and analyzing performance. Work together with global teams from different functions and undergo enhanced quality checks for our library work. Engage with customers to understand new library requirements and identify PPA (Power, Performance, Area) knobs through DTCO solutions. Communicate effectively with customers to ensure that all project milestones are met on time. Track and prioritize tasks across multiple event releases and efforts simultaneously.

#designenablement

Qualifications:
Required skills/experience:

• A high performer with 12+ years of demonstrable experience in most of the standard cell library domains such as circuit design, std cell layouts, extraction, characterization, modeling, physical view abstraction, logic view modeling, reliability and IR drop characterization, validation, quality assurance, documentation and library releases including customer support.
• Deep working knowledge of digital logic design and standard cell library development in advanced nodes.
• Demonstrated ability to understand and interpret industry benchmarks, create and drive strategies, work independently, and simultaneously manage diverse and extensive assignments while remaining organized and productive in a complex environment.
• Strong self-initiative, persistence, and ability to deal with a high degree of ambiguity and task and deadline pressure.
• Strong written and verbal communication skills. Ability to synthesize abstract complex information into clear messages to create impactful presentations.

Preferred skills/experience:

• In-depth knowledge in digital design including CMOS combinatorial logic and sequential circuit and layout, and familiarity with design tradeoffs as well as standard cell modeling, extraction, and characterization highly desired.
• Familiar with foundry ecosystem and benchmarking practice. Technical, analytical, customer-oriented, and cross-functional collaboration skills.
• Ability to work in a dynamic and matrix team-oriented environment.
• Experience in designing flips flops, clock gating cells, level shifters, power gating cells and other complex circuits.
• Clear understanding of CMOS device characteristics and design rules in submicron process nodes. Knowledge of submicron process issues, especially in FINFET technologies. Familiarity in high sigma variation analysis in smaller technology nodes.
• Experience in standard cell circuits optimization to achieve better PPA. Familiarity with layout design and experience in working with layout designers to optimize layout parasitic to achieve target PPA.
• Involvement in layout extraction and understanding of layout dependent parameters in the extracted netlist.
• Understanding of timing/leakage characterization of Standard cells.
• Scripting capability in TCL/PERL/Python. Strong Analytical and Logical skills.

#DesignEnablement

          

Job Type:
Experienced Hire

Shift:
Shift 1 (Malaysia)

Primary Location:
Malaysia, Penang

Additional Locations:

Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Job Details:

Job Description:
Foundational IP team under Foundry Design Technology Platform group has primary focus of Standard Cell Library development to support both Intel Product Teams and External customers. The team is looking for a highly motivated and experienced individual to lead the library development, and optimization of standard cell libraries to enable best-in-class IP and product design on all generations of Intel technology.

Responsibilities include but are not limited to the following:

• Leads and manages the strong and vital organization of the Standard Cell Library team in Malaysia that spans across all functions of the Standard Cell Library organization.
• Collaborates and work closely with the Standard Cell Library Staff members who own various libraries and functions.
• Responsible for enabling teams to execute through clear goal setting, facilitating work, maintaining accountability, driving team results, and applying differentiated performance management.
• Works to continuously improve organization and development processes across all areas of design to improve efficiency and achieve quality standards.

As a technical lead, you are responsible for leading the standard cell library development and optimization activities with active collaboration with process technologists, product design and IFS stakeholders, and EDA vendors to achieve best-in-class cell/block level PPA and competitive EoU (Ease of Use) through DTCO (Design-Technology Co-Optimization).

Assume a leadership role managing a group of engineers, leaders, and managers in circuit design development, layout design development, extraction/characterization execution activities, FE/BE modeling, reliability/IR drop characterization, driving automation, and standardization of standard cell library development and validation flows. Supporting development and delivery of various process and PDK (Process Design Kits) production standard cell contents.

Our goal is to define, design, develop, and deliver best-in-class production standard cell libraries. Work on designing and characterizing standard cell libraries in the latest technology node, while also advancing the concepts of circuit design at the transistor level, as well as modeling and analyzing performance. Work together with global teams from different functions and undergo enhanced quality checks for our library work. Engage with customers to understand new library requirements and identify PPA (Power, Performance, Area) knobs through DTCO solutions. Communicate effectively with customers to ensure that all project milestones are met on time. Track and prioritize tasks across multiple event releases and efforts simultaneously.

#designenablement

Qualifications:
Required skills/experience:

• A high performer with 12+ years of demonstrable experience in most of the standard cell library domains such as circuit design, std cell layouts, extraction, characterization, modeling, physical view abstraction, logic view modeling, reliability and IR drop characterization, validation, quality assurance, documentation and library releases including customer support.
• Deep working knowledge of digital logic design and standard cell library development in advanced nodes.
• Demonstrated ability to understand and interpret industry benchmarks, create and drive strategies, work independently, and simultaneously manage diverse and extensive assignments while remaining organized and productive in a complex environment.
• Strong self-initiative, persistence, and ability to deal with a high degree of ambiguity and task and deadline pressure.
• Strong written and verbal communication skills. Ability to synthesize abstract complex information into clear messages to create impactful presentations.

Preferred skills/experience:

• In-depth knowledge in digital design including CMOS combinatorial logic and sequential circuit and layout, and familiarity with design tradeoffs as well as standard cell modeling, extraction, and characterization highly desired.
• Familiar with foundry ecosystem and benchmarking practice. Technical, analytical, customer-oriented, and cross-functional collaboration skills.
• Ability to work in a dynamic and matrix team-oriented environment.
• Experience in designing flips flops, clock gating cells, level shifters, power gating cells and other complex circuits.
• Clear understanding of CMOS device characteristics and design rules in submicron process nodes. Knowledge of submicron process issues, especially in FINFET technologies. Familiarity in high sigma variation analysis in smaller technology nodes.
• Experience in standard cell circuits optimization to achieve better PPA. Familiarity with layout design and experience in working with layout designers to optimize layout parasitic to achieve target PPA.
• Involvement in layout extraction and understanding of layout dependent parameters in the extracted netlist.
• Understanding of timing/leakage characterization of Standard cells.
• Scripting capability in TCL/PERL/Python. Strong Analytical and Logical skills.

#DesignEnablement

          

Job Type:
Experienced Hire

Shift:
Shift 1 (Malaysia)

Primary Location:
Malaysia, Penang

Additional Locations:

Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.